Efficient Modular Adders for Scalable Encryption Algorithm

SEA – Scalable Encryption Algorithm is a block cipher based symmetric encryption scheme, specially designed for resource constrained devices. SEA proposes low computational encryption routines (i.e. less code size, memory and power) for processors with a restricted instruction set. SEA is parametric with plain-text, key and microprocessor size, and meant for efficient combination of encryption/decryption and key derivation. The performance of modified SEA using efficient architectures of 2 and 2-1 modular adders in a Field programmable gate array (FPGA) device is investigated. In this paper, an iterative based loop design of the block cipher is first implemented on FPGA. The proposed modular adders in SEA achieve lower area and power consumption on the target platform VIRTEX-4, xc4vl25-10ff668. Beyond its low cost performances, the proposed architecture is fully flexible with any parameters and takes advantage of generic VHDL coding.